DDR4+ | DDR3 | Single ended JEDEC HSTL | Low Power | Low Area | Low Pincount | High SI

Patented Low Power High Bandwidth Single-ended DDRx Tx

Multi-level Pre-emphasis, Low latency, Variable data widths, JEDEC HSTL standard

Patented Low Swing High Bandwidth Single-ended DDRx Rx

Low Swing, Low latency, Variable data widths, JEDEC HSTL standard

Patented High Speed Fine Grain Dynamic Timing Alignment and Re-synchronizer

Low jitter, 64 phase, Fine-grain, High resolution Timing Alignment Engine

Patented Automated On Die Impedance Termination for DDRx IO

Automated, PVT invariant, Wide range (35-70 Ohms) board/package trace impedance matching

Patented Low Power Multi-Phase Timing Unit for DDR4 single-ended IO

Low Power, Low Jitter, Wide range On-Chip PLL and DLL

Signal Integrity

ISI, SSO, Crosstalk, Clock Jitter, Pwr/gnd bounce, ESD, EMI, PVT, Pkg/Board via/trace/RLC

Reference Design

FR4, multi-layer, 3"/5"/15" traces, 3/5 vias, chip-chip, chip-connector-chip, chip-DIMM-chip, Design/Simulation models, Schematic/GDSII/HDL DB, P&R and SI guidelines, Test/characterization guidelines, Package/Board design guidelines, COT/ASIC flow integration guidelines.

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