Venture backed fab-less semiconductor company

Low Power High Bandwidth Single-ended TxPHY

1pin/bit, 2.5Gbps/pin, Multi-level Pre-emphasis, JEDEC HSTL standard, DDR3 Compliant

Low Power High Bandwidth Single-ended RxPHY

1pin/bit, 2.5Gbps/pin, Low Swing (100mv pp), JEDEC HSTL standard, DDR3 Compliant

Dynamic Timing Alignment and Re-synchronizer

Low jitter, multi-phase (64), multi-grain, high resolution (12ps) timing alignment, DDR3 Compliant

Automated On Die Impedance Termination

Automated, PVT invariant, Wide range (35-70 Ohms) trace impedance matching, DDR3 Compliant

Low Power Multi-Phase Clock Generator

Low Power, Low Jitter, Wide output range (300MHz-1.25GHz), Low frequency input clock, PLL, DLL

Mobile Memory/Logic MCP

Low power, pincount, Low footprint, Multi Die MCP for mobile devices

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